The design of the controller consists of an FPGA, analog-to-digital converter & toggle switches for the inputs, motor and LCD for the input. A block diagram for the controller is shown in Figure 2.
The hardware consists of one 20 character by 4 line LCD screen, potentiometers for acceleration and braking, battery, ADC 0808, motor, IR sensor, PWM driver circuit and five toggle switches. Figure 3 shows the hardware interface for the design. To get the acceleration data, a 47K potentiometer is used. Likewise, another potentiometer is used to get the brake data. A lead acid battery of 12V 7.5 AH is used to give the power supply to the whole module. A voltage regulator circuit is used to provide the 5V that is needed from the 12V available to other components in the circuit. The voltage for the motor (12 V) is taken directly from the battery and a voltage regulator circuit is used to step down the 12V to 5 V in order to drive the Xilinx, ADC and LCD components. The ADC 0808 is an 8-channel, 8-bit analog to digital converter from National Semiconductor. Its operating voltage is 5V DC with 100^s conversion times. A 12V DC motor of 2400 rpm is used. In total five toggle switches are used; three switches are used for the gear selection. Among the eight combinations, 000 represents neutral, 001 is for 1st, 010 is for 2nd, 011 is for 3rd, 110 is for 4th, 101 is for reverse gear and the other left out combinations remain unused. Another two switches are for terrain (00-smooth, 01-rough, 10-uphill, and 11-downhill) selection. The speed of the motor will differ for each terrain based on the other inputs. A separate battery charger circuit is designed using bridge rectifier and LM317 voltage regulator for the offline battery charging. A power supply circuit is designed using LM7805 voltage regulator to convert the 12V to 5 V in order to drive the Xilinx, ADC and LCD components.
Data Acquisition Unit
The data acquisition unit drives the ADC 0808 to get the crisp inputs (acceleration, braking & state of charge). The analog inputs are taken from potentiometers of from the battery. The analog values have to be converted into digital values before being given to the FPGA. Therefore, analog to digital converter (ADC 0808) chip is used. The ADC 0808 chip allows monitoring up to 8 different transducers using only one chip. Here, only three channels are used to get the acceleration, braking and state of charge of the battery. The 8 analog inputs channels are multiplexed and selected using the address pins A, B and C.
The A, B and C address to select IN0 – IN7 and activate ALE (Address Latch Enable) to latch in the address. START is for start of conversion. EOC is for End of Conversion and OE is for Output Enable (READ). The following steps are to be carried out for data conversion by the ADC 0808 chip:
1. Select an analog channel by providing bits to A, B and C addresses (000 -acceleration, 001 – braking and 010 – for battery).
2. Activate the ALE (Address Latch Enable) pin. It needs an L to H pulse to latch inthe address.
3. Activate START by an H to L pulse to initiate conversion.
4. Check the EOC to see whether conversion is finished. H to L output indicates that the data is converted and is ready to be read.
5. An H to L pulse to the OE pin will read 8 bit data out.
All the above steps have to be carried out at the 8 KHz clock frequency. Therefore, a VHDL clock divider module is written to generate the 8 KHz clock for the data conversion since the conversion time is approximately 100^s. Figure 4 shows the signals, which are involved in the conversion of analog data to digital. Here, channel IN0 is used for the acceleration input, channel IN1 is used for braking, channel IN2 is used for the battery input and the remaining channels are left unused. Therefore, the multiplexing is done only for the first three channels.
The generation of the control signals and addresses for the channel selection at the appropriate moments and reading the 8-bit digital data are coded in VHDL using the finite state machine. The Mealy type state machine is used. In this type of state machine, the outputs not only depend on the state of the machine but also on its inputs. This type of machine can be modeled by using two processes in VHDL coding, one process that models the synchronous aspect of the finite state machine and one that models the combination part.
Implantation of Fuzzy Controller
The components of the fuzzy controller for the DC motor are implemented in VHDL . The specifications for the implementation of the FLC are; number of input variables = 6, number of output variable = 1, number of bits required to represent the input variables =8, number of fuzzy sets for the variables vary from 3 to 6 and all the variables use to non overlapping rectangular membership functions. The input parameters are 1) Speed 2) Acceleration 3) Braking 4) State of charge of battery 5) Gear and 6) Terrain. The output of the fuzzy system is the duty cycle of the PWM signal. In this controller design, the speed is taken in the range of 00-FF. The range is divided into three linguistic variables namely short, medium and high. The Gear is taken in the range of 0-6. The range is divided into five linguistic variables namely Neutral, 1st gear, 2nd gear, 3rd gear, 4th gear and Reverse. The State of charge of the battery is taken in the range of 00-FF. The range is divided into three linguistic variables namely low, normal and high. The Terrain is taken in the range of 1-4. The range is divided into four linguistic variables namely Smooth, Rough, Uphill and Downhill. The output parameter duty cycle of the PWM signal is taken in the range of 00-64. The range is divided into four linguistic variables namely very low, low, medium and high.
The implementation process is subdivided into three components namely fuzzifier, rule base and defuzzifier. The complete structures of the fuzzy controller with other blocks are shown in figure 5. the function of the fuzzifier is to transform crisp inputs into fuzzy inputs. Crisp inputs for the accelerator, brake and battery are 8-bit binary value representing the current reading, 3-bit binary value for gear, 2-bit binary value for gear and stream of pulses for speed. The first step is to convert the crisp inputs to fuzzy inputs; for those, compare the crisp inputs with the membership function parameters of variables respectively. Rule evaluation is the second step of the fuzzy logic process, and determines what control action should occur in response to a given set of input values. A rule base for this system is created as shown in table 1, 2, 3, 4. Totally, there are 70 rules written for this design. Sample lists of rules are shown in the matrix format. The rule evaluation method used is “min-max” inferences, since it takes the minimum of the antecedents to determine rule strength and the maximum of the rule strengths for each consequent to determine fuzzy outputs.
When Terrain – Sm, Gear – 4,
Table 1 : Rule base for smooth terrain
When Terrain -R ,Gear-4
Table 2 : Rule base for rough terrain
When Terrain -U, Gear-4
Table 3 : Rule base for uphill terrain
When Terrain -D, Gear-4
Table 4 : Rule base for downhill terrain
Defuzzification is the last step in fuzzy logic process, which transforms the fuzzy outputs to crisp output based on the output membership function. In defuzzification, all significant outputs will be combined into a specific, comprehensive result to get crisp output. One of the most common defuzzification techniques called center of gravity or centroid method is used here.
PWM Driver Unit
In this unit, the output from the fuzzy controller to the motor is considered. The input to the motor can be given in terms of the pulse width modulation signal. Since this system has been designed as closed-loop, the feedback from the motor has to be taken. A feedback device’s basic function is to transform a physical parameter into an electrical signal for use by a motion controller. Common feedback devices are encoders for position feedback, tachometers for velocity feedback, and accelerometers for acceleration feedback. Among the above-mentioned ways to measure the speed of the motor, the optical encoder technique is used here. The crisp output from the defuzzifier is given to the pulse width generator to generate the PWM signal to drive the motor. The motor is connected to the FPGA through the driver circuit as shown in figure 6. Actually, this PWM signal is given as a gate signal to the MOSFET in the drive unit, which in turn drives the motor, depending upon the duty cycle of the signal.
A totem pole transistor is used before the MOSFET to decide whether the MOSFET is to be turned on or off. Also, the direction of rotation (i.e.) clockwise or anticlockwise direction is decided by the control signal, which is generated by the FPGA. When the gear is chosen to be reverse, then the control signal is set to 0 to make the motor rotate in the anticlockwise direction. Otherwise, this control signal is set to 1 for all other gears to make the motor rotate in clockwise direction. For achieving this operation, a relay coil with DPDT switch is used. For 100% duty cycle, the motor runs at its maximum speed and for 10%, it runs at its lowest speed. The PWM signal is generated with reference to the external clock signal. Since the motor is running at a speed of 100 Hz, the PWM signal is generated at this frequency. The on and off period of the PWM signal is varied with reference to the generated clock frequency. These feedback signals from the motor that are generated are then fed into the controller where pulses are counted based on the signals received and the speed is determined internally to decide the speed for the successive moments for the motor.
The function of the display unit is to display the terrain type, gear chosen, accelerator status, braking status, battery charge status and speed of the motor in Liquid Crystal Display (LCD). In order to display any information in LCD, first it has to be first initialized and then the data is sent. The one factor to be considered here is sending the information to LCD in terms of ASCII. So the LCD module has to change the decimal value to ASCII or std_logic_vector to ASCII respectively. Three control signals such as Enable, Register Select and Read/Write are generated from the FPGA and given to LCD. And, ASCII values are passed to LCD through 8-bit data lines. Figure 7 shows the interfacing of LCD with FPGA.
Here, 20 * 4 LCD display is used. To display any information in any row, the appropriate row address has to be selected and the cursor has to be removed there. The cursor address for this LCD is given below.
80 81 82 ………. 93 — 1st row
C0 C1 C2………D3 —- 2nd row
94 95 96 ………..A7 — 3rd row
D4 D5 D6………E7 — 4th row
To initialize the LCD, the following steps have to be carried out for the initialization process, waiting for required period of time after the execution of each step.
1. Send 38h to LCD for function set
2. Send 0Eh for display on and cursor on
3. Send 01h for clear display
4. Send 1Ch for shift the entire display to the right
5. Send 02h for return home
Then, send the row address to LCD and the information to display. The required clock for this module is generated internally with reference to the external clock.